XConn Technologies has unveiled its Apollo 2 hybrid switch, integrating both Compute Express Link (CXL) 3.1 and PCIe Gen 6.2 on a single chip.

Designed to meet AI, machine learning, and high-performance computing (HPC) demands, the new interconnect offering supports the latest standards for both CXL and PCIe protocols across configurations ranging from 64 to 260 lanes.

In a statement, XConn said Apollo 2 sets a “new benchmark in flexibility and performance” for next-generation computing environments, with the company’s hybrid approach providing “optimal compatibility and memory performance enhancements across various computing platforms.”

Founded in 2020, privately funded XConn launched the industry’s first CXL 2.0 and PCIe Gen 5.0 switch chip, Apollo, in March 2024. Produced by TSMC using the chipmaker’s N16 and N5 technologies, that interconnect provides 256 lanes with a total of 2,048Gbps switching capacity.

“Building on the success of our Apollo 1 switch, the Apollo 2 switch represents a significant advancement in our technology roadmap,” said Gerry Fan, CEO of XConn Technologies. “This switch not only meets the latest standards of CXL and PCIe but also provides unprecedented density and scalability, which are crucial for the evolving demands of modern data centers and computing architectures.”

Established in 2019, CXL is an open standard interconnect specification based on technology developed by Intel.

CXL was developed to improve performance and remove bottlenecks between CPUs and other components like GPUs, memory, and FPGAs. Alongside the technology exists the CXL Consortium, a group established to help advance the technology of which XConn is a member.

DCD spoke to XConn Technologies for our latest Networking Supplement.