AMD has unveiled its 6th generation Epyc processor, codenamed Venice, which the company says is the first HPC CPU to be taped out on TSMC’s 2nm (N2) process technology.

The chipmaker also announced the bring up and validation of its 5th generation Epyc CPUs – previously known as Turin – at TSMC’s new chip fab in Arizona.

Based on the Zen 5 architecture, the 5th gen Epyc CPU was launched in October 2024. The CPU offers a core count from eight to 192. AMD claims that the chip’s architecture provides up to 17 percent better instructions per clock (IPC) for enterprise and cloud workloads, and up to 37 percent higher IPC in AI and high-performance computing (HPC) compared to Zen 4.

No details about the Venice chip family have been announced yet, but the CPU is expected to be launched in 2026.

“TSMC has been a key partner for many years, and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said Dr. Lisa Su, chair and CEO, AMD. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”

TSMC chairman and CEO Dr. C.C. Wei added: “We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon.”

The news comes in the same week that Nvidia announced plans to produce AI supercomputers 'entirely' in the US, saying it would work with its manufacturing partners to commission more than a million square feet of manufacturing space to build and test Blackwell GPUs in Arizona and AI supercomputers in Texas.